The present invention relates to a semiconductor memory device using nonvolatile memory cells known as MONOS cells designed to store electric charges in nitride films.
A MONOS type nonvolatile memory cell has a cell transistor structure in which a nitride film sandwiched between a pair of insulating films, e.g., oxide films, is formed between the channel portion and gate electrode of the cell transistor, and electrons as electric charges can be stored in the nitride film.
When electrons are stored or trapped in this nitride film, the electric field applied from the gate electrode upon application of a voltage thereto is canceled out in accordance with the amount of electrons stored in the nitride film. This allows the threshold voltage of the cell transistor in which electrons are stored to differ from that of a cell transistor in which no electrons are stored. Data is recorded and read by using this transistor's property of being able to make threshold voltages differ from each other.
In a general semiconductor memory device using MONOS type memory cell transistors, for example, in a data write operation, the drain and source of a selected memory cell transistor are respectively biased to the write potential and the Vss potential. In this case, the sources and drains of all memory cell transistors other than the selected memory cell transistor are set at the floating potential. For this reason, the source potential of an unselected memory cell transistor adjacent to the drain side of the selected memory cell transistor is lower than the drain voltage of the selected memory cell transistor, a current flows from the drain to the source of the adjacent unselected memory cell transistor. As a result, the nitride film of the unselected memory cell transistor is charged, and hence a write error occurs. In general, when data is to be written, the drain potential of the selected cell transistor is set to be higher than the source potential of each adjacent unselected cell transistor. For this reason, a current may flow from this selected cell transistor to two or three adjacent unselected cell transistors in addition to the selected cell transistor.
Obviously, such a phenomenon also occurs in a data read operation.
It is, therefore, an object of the present invention to provide a MONOS nonvolatile semiconductor memory device which can prevent write and read errors in unselected memory cell transistors adjacent to a selected memory cell transistor in data write and read operations.